Clash: structure descriptions of synchronous hardware using haskell

[2015-03-17 Tue 19:38] speaker: Michal Gajda event: Papers We Love SG #007 ** FPGA ASICS need to be made in bulk, but lower cost per unit FPGA is higher cost per unit and higher power consumption ** Clash is a GHC plugin hardware dsl in haskell that is compiled to VHDL

• functional testing by executing the code

• no timing analysis